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COMMUNICATION SEMICONDUCTORS
MX919B
4-Level FSK Modem Data Pump
PRELIMINARY INFORMATION
DATA BULLETIN
Features
* * * * * * * * 4-Level Root Raised Cosine FSK Modulation Half Duplex, 4800 to 19.2kbps Increase Channel Bit Rate/Hz Full Data Packet Framing Impulse and NRZ Signal Modes Enhanced Performance in Noisy Conditions Error Detection and Error Correction Low Power 3.3V/5.0V Operation
Applications
* * * * * Wireless Data Terminals Two Way Paging Systems Digital Radio Systems Wide Area Wireless Data Broadcasts Point to Point Wireless Data Links
RADIO
MODULATOR RF DISCRIMINATOR ANALOG RX ANALOG TX
MX919B
MODEM DATA PUMP
DATA AND CONTROL BUS
HOST C
SYSTEM APPLICATION PROCESSING
The MX919B is a low voltage CMOS device containing all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host C and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over a wireless link. The MX919B assembles application data received from the host C, adds forward error correction (FEC) and error detection (CRC) information, and interleaves the result for burst-error protection. After automatically adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for modulating the radio transmitter. In receive mode, the MX919B performs the reverse function using the analog signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the host C. CRC detected residual uncorrected data errors will be flagged. A readout of the SNR value during receipt of a packet is also provided. The MX919B uses data block sizes and FEC/CRC suitable for applications where high-speed transfer of data over narrow-band wireless links is required. The device is programmable to operate at standard bit rates from a wide range of Xtal/clock frequencies. The MX919B may be used with a 3.0V to 5.5V power supply and is available in the following package styles: 24-pin SSOP (MX919BDS), 24-pin SOIC (MX919BDW), 24-pin PLCC (MX919BLH), and 24-pin PDIP (MX919BP).
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 2 of 47
MX919B PRELIMINARY INFORMATION
CONTENTS
Section Page
1. Block Diagram ............................................................................................................... 6 2. Signal List ...................................................................................................................... 7 3. External Components ................................................................................................... 8 4. General Description ...................................................................................................... 9
4.1 Description of Blocks ......................................................................................................... 9
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 Data Bus Buffers..................................................................................................................... 9 Address and R/W Decode ...................................................................................................... 9 Status and Data Quality Registers.......................................................................................... 9 Command, Mode, and Control Registers ............................................................................... 9 Data Buffer.............................................................................................................................. 9 CRC Generator/Checker ........................................................................................................ 9 FEC Generator/Checker ......................................................................................................... 9 Interleave/De-Interleave Buffer............................................................................................... 9 Frame Sync Detect ................................................................................................................. 9
4.1.10 Rx Input Amp ........................................................................................................................ 10 4.1.11 RRC Low Pass Filter ............................................................................................................ 10 4.1.12 Tx Output Buffer.................................................................................................................... 11 4.1.13 Rx Level/Clock Extraction..................................................................................................... 12 4.1.14 Clock Oscillator and Dividers................................................................................................ 12
4.2 4.3 4.4 4.5
Modem - C Interaction ................................................................................................... 12 Binary to Symbol Translation ........................................................................................... 13 Frame Structure............................................................................................................... 14 The Programmer's View................................................................................................... 15
4.5.1 4.5.2 Data Block Buffer .................................................................................................................. 15 Command Register ............................................................................................................... 15 Command Register B7: AQSC - Acquire Symbol Clock ................................................ 16 Command Register B6: AQLEV - Acquire Receive Signal Levels ................................. 16 Command Register B5: CRC ........................................................................................ 16 Command Register B4: TXIMP - Tx Level/Impulse Shape ............................................ 16 Command Register B3 - Reserved ................................................................................ 16 Command Register B2, B1, B0: TASK........................................................................... 16 NULL: No effect .............................................................................................................. 18 SFSH: Search for Frame Sync plus Header Block ........................................................ 18 RHB: Read Header Block............................................................................................... 18
4.5.2.1 4.5.2.2 4.5.2.3 4.5.2.4 4.5.2.5 4.5.2.6 4.5.2.7 4.5.2.8 4.5.2.9
4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block ....................................................................... 18 4.5.2.11 SFS: Search for Frame Sync ......................................................................................... 18 4.5.2.12 R4S: Read 4 Symbols .................................................................................................... 19 4.5.2.13 T24S: Transmit 24 Symbols ........................................................................................... 19 4.5.2.14 THB: Transmit Header Block.......................................................................................... 19 4.5.2.15 TIB: Transmit Intermediate Block ................................................................................... 20 4.5.2.16 TLB: Transmit Last Block ............................................................................................... 20
(c)2001 MX*COM, INC. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 3 of 47
MX919B PRELIMINARY INFORMATION
4.5.2.17 T4S: Transmit 4 Symbols ............................................................................................... 20 4.5.2.18 RESET: Stop any current action .................................................................................... 20 4.5.2.19 Task Timing .................................................................................................................... 20 4.5.2.20 RRC Filter Delay............................................................................................................. 21 4.5.3 Control Register .................................................................................................................... 22 Control Register B7, B6: CKDIV - Clock Division Ratio ................................................. 22 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches............. 22 Control Register B3, B2: LEVRES - Level Measurement Modes .................................. 23 Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes .................. 23 Mode Register B7: IRQEN - IRQ Output Enable ......................................................... 24 Mode Register B6: INVSYM - Invert Symbols................................................................ 24 Mode Register B5: TX/RX - Tx/Rx Mode ...................................................................... 24 4.5.3.1 4.5.3.2 4.5.3.3 4.5.3.4 4.5.4 4.5.4.1 4.5.4.2 4.5.4.3
Mode Register....................................................................................................................... 24
4.5.4.4 4.5.4.5 4.5.4.6 4.5.5 4.5.5.1 4.5.5.2 4.5.5.3 4.5.5.4 4.5.5.5 4.5.5.6 4.5.6
Mode Register B4: RXEYE - Show Rx Eye.................................................................... 25 Mode Register B3: PSAVE - Powersave........................................................................ 25 Mode Register B2, B1, B0 .............................................................................................. 25 Status Register B7: IRQ - Interrupt Request .................................................................. 26 Status Register B6: BFREE - Data Block Buffer Free.................................................... 26 Status Register B5: IBEMPTY - Interleave Buffer Empty............................................... 26 Status Register B4: DIBOVF - De-Interleave Buffer Overflow ....................................... 26 Status Register B3: CRCERR - CRC Checksum Error.................................................. 27 Status Register B2, B1, B0............................................................................................. 27
Status Register ..................................................................................................................... 26
Data Quality Register............................................................................................................ 27 Cyclic Redundancy Codes.................................................................................................... 27 CRC1 .............................................................................................................................. 27 CRC2 .............................................................................................................................. 28 Forward Error Correction................................................................................................ 28 Interleaving ..................................................................................................................... 28
4.6
CRC, FEC, and Interleaving............................................................................................. 27
4.6.1 4.6.1.1 4.6.1.2 4.6.1.3 4.6.1.4
4.7 5.1 5.2 5.3
Transmitted Symbol Shape.............................................................................................. 28 Transmit Frame Example................................................................................................. 30 Receive Frame Example.................................................................................................. 33 Clock Extraction and Level Measurement Systems.......................................................... 36
5.3.1 5.3.2 5.3.3 5.3.4 Supported Types of Systems................................................................................................ 36 Clock and Level Acquisition Procedures with RF Carrier Detect ......................................... 36 Clock and Level Acquisition Procedure without RF Carrier Detect ...................................... 36 Automatic Acquisition Functions........................................................................................... 37
5. Application................................................................................................................... 30
5.4 5.5 5.6
AC Coupling..................................................................................................................... 37 Radio Performance .......................................................................................................... 39 Received Signal Quality Monitor ...................................................................................... 40
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 4 of 47
MX919B PRELIMINARY INFORMATION
6. Performance Specification ......................................................................................... 41
6.1 Electrical Performance..................................................................................................... 41
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Absolute Maximum Ratings .................................................................................................. 41 Operating Limits.................................................................................................................... 41 Operating Characteristics ..................................................................................................... 42 Operating Characteristics Notes: ................................................................................... 42 Timing ................................................................................................................................... 43 Typical Bit Error Rate............................................................................................................ 45
6.1.3.1
6.2
Packaging........................................................................................................................ 46
MX-COM, Inc. Reserves the right to change specifications at any time and without notice
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 5 of 47
MX919B PRELIMINARY INFORMATION
Figures
Figure Page
Figure 1: Block Diagram ..................................................................................................................................... 6 Figure 2: Recommended External Components ................................................................................................ 8 Figure 3: Typical Modem C connections .......................................................................................................... 9 Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode................................................. 10 Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5).................... 11 Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)............ 11 Figure 7: Over-Air Signal Format ..................................................................................................................... 14 Figure 8: Alternative Frame Structures ............................................................................................................ 15 Figure 9: Transmit Task Overlapping ............................................................................................................... 17 Figure 10: Receive Task Overlapping .............................................................................................................. 17 Figure 11: Transmit Task Timing Diagram ....................................................................................................... 21 Figure 12: Receive Task Timing Diagram ........................................................................................................ 21 Figure 13: RRC Low Pass Filter Delay............................................................................................................. 21 Figure 14: Ideal 'RXEYE' Signal....................................................................................................................... 25 Figure 15: Typical Data Quality Reading vs S/N .............................................................................................. 27 Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1 ........................................................... 28 Figure 17: Tx Signal Eye TXIMP = 0 ................................................................................................................ 29 Figure 18: Tx Signal Eye TXIMP = 1 ................................................................................................................ 29 Figure 19: Transmit Frame Example Flowchart, Main Program ...................................................................... 31 Figure 20: Tx Interrupt Service Routine ........................................................................................................... 32 Figure 21: Receive Frame Example Flowchart, Main Program ........................................................................ 34 Figure 22: Rx Interrupt Service routine ............................................................................................................ 35 Figure 23: Acquisition Sequence Timing.......................................................................................................... 36 Figure 24: Effect of AC Coupling on BER (without FEC) ................................................................................. 37 Figure 25: Decay Time - AC Coupling.............................................................................................................. 38 Figure 26: Typical Connections between Radio and MX919B......................................................................... 39 Figure 27: Received Signal Quality Monitor Flowchart .................................................................................... 40 Figure 28: C Parallel Interface Timings.......................................................................................................... 44 Figure 29: Typical Bit Error Rate With and Without FEC ................................................................................. 45 Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW ................................................. 46 Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS ................................................. 46 Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH ................................................. 47 Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP ..................................................... 47
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 6 of 47
MX919B PRELIMINARY INFORMATION
1. Block Diagram
IRQ 8 D0 D1 D2 D3 D4 D5 D6 D7 WR RD CS A0 A1
VDD VDD
STATUS REGISTER
DATA QUALITY REGISTER
CONTROLLER INTERFACE
DATA BUS BUFFERS
COMMAND REGISTER
MODE REGISTER
CONTROL REGISTER
DATA BUFFER
CRC GENERATOR/ CHECKER
ADDRESS AND R/W DECODE
FEC ENCODER/ DECODER
INTERLEAVE/ DE-INTERLEAVE
FRAME SYNC DETECT
VBIAS Tx Symbols VSS Rx Symbols
RXAMPOUT Rx Input Amp VBIAS RXIN XTAL CLOCK OSCILLATOR AND DIVIDERS XTAL / CLOCK Rx
Tx RRC LOW PASS FILTER VBIAS Rx Tx Rx Tx
DOC1 Rx LEVEL/CLOCK EXTRACTION RxEye TXOUT Tx Output Buffer DOC2
Figure 1: Block Diagram
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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4-Level FSK Modem Data Pump
Page 7 of 47
MX919B PRELIMINARY INFORMATION
2. Signal List
Pin No. 1 Signal
IRQ D7 D6 D5 D4 D3 D2 D1 D0
RD WR
Type output
Description A 'wire-ORable' output for connection to the host C's Interrupt Request input. When active, this output has a low impedance pull down to VSS. It has high impedance when inactive.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BUS BUS BUS BUS BUS BUS BUS BUS input Input power input input input output input output output output output input output power
Pins 2-9 (D7-D0) are 8-bit, bi-directional, 3-state C interface data lines
VSS CS A0 A1
XTAL XTAL/CLOCK DOC2
Read. An active low logic level input used to control the reading of data from the modem into the host C. Write. An active low logic level input used to control the writing of data into the modem from the host C. Negative supply (ground). Chip Select. An active low logic level input to the modem used to enable a data read or write operation. Logic level modem register select input Logic level modem register select input Output of the on-chip oscillator. Input to the on-chip oscillator, for an external Xtal circuit or clock. Connection to the Rx level measurement circuitry. Should be capacitive coupled to VSS . Connection to the Rx level measurement circuitry. Should be capacitive coupled to VSS Tx signal output from the modem. A bias line for the internal circuitry held at VDD/2. This pin must be bypassed to VSS by a capacitor mounted close to the device pins. Input to the Rx input amplifier. Output of the Rx input amplifier. Positive supply. Levels and voltages are dependent upon this supply. This pin should be bypassed to VSS by a capacitor mounted close to the device pins.
Table 1: Signal List
DOC1 TXOUT VBIAS RXIN RXAMPOUT VDD
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
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Doc. # 20480170.003
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4-Level FSK Modem Data Pump
Page 8 of 47
MX919B PRELIMINARY INFORMATION
3. External Components
VDD C1 C8 R2 R1 From Rx FM Discriminator To Tx Frequency Modulator
CONTROLLER INTERFACE
IRQ D7 D6 D5 D4 D3 D2 D1 D0 RD WR CS A0 A1
1 2 3 4 5 6 7 8 9 10 11 12
MX919B
VSS
24 23 22 21 20 19 18 17 16 15 14 13
VDD
RXAMPOUT RXIN VBIAS TXOUT DOC1 DOC2 XTAL/CLOCK XTAL A1 A0 CS
R4
C7
C6
C5
C2
17
XTAL/CLOCK
X1 R3
XTAL
C3 C4
16
Figure 2: Recommended External Components
Component R1 R2 R3 R4 C1 C2 C3 3 Notes 3 100k 1M 100k 0.1F 0.1F Value Tolerance 20% 5% 20% 5% 20% 20% 20% X1 2,3 Component C4 C5 C6 C7 C8 Notes 3 4 5 5 4 Value Tolerance 20% 5% 20% 20% 5%
Table 2: Recommended External Components Recommended External Component Notes: 1. See Section 4.1.10. 2. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. 3. The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide, values (including stray capacitance) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable. Crystal frequency tolerances are discussed in Section 4.5.3.4. 4. Values C5 and C8 should be equal to 750,000 / symbol rate, e.g. 5. Values C6 and C7 should be equal to 50,000 / symbol rate, e.g.
Symbol Rate 2400 symbols/second 4800 symbols/second 9600 symbols/second C5 and C8 330pF 150pF 82pF Symbol Rate 2400 symbols/second 4800 symbols/second 9600 symbols/second C6 and C7 0.022F 0.01F 4700pF
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 9 of 47
MX919B PRELIMINARY INFORMATION
4. General Description
4.1 4.1.1 Description of Blocks Data Bus Buffers
Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host C's data bus lines.
4.1.2 Address and R/W Decode
This block controls the transfer of data bytes between the C and the modem's internal registers according to the state of the Write and Read Enable inputs ( WR and RD ), the Chip Select input ( C S ), and the Register Address inputs A0 and A1. The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel C interface, which can be memory-mapped, as shown in Figure 3.
D0:7 A0:1 D0:7 A0:1
Data Bus Address Bus
Address Decode Circuit
A2:7
CS
C
IRQ WR RD
VDD IRQ pull up resistor
MODEM
IRQ WR RD
Figure 3: Typical Modem C connections 4.1.3 4.1.4 4.1.5 4.1.6 Status and Data Quality Registers Command, Mode, and Control Registers Data Buffer CRC Generator/Checker
Two, 8-bit registers which the C can read, to determine the status of the modem and received data quality. The values written by the C to these 8-bit registers control the operation of the modem. A 12-byte buffer used to hold receive or transmit data to or from the C. A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum bits, which may be included in the transmitted data blocks so the receive modem can detect transmission errors.
4.1.7 FEC Generator/Checker
In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the conversion of binary data to 4-level symbols. In receive mode, this circuit translates received 4-level symbols to binary data, using the FEC information to correct a large proportion of transmission errors.
4.1.8 Interleave/De-Interleave Buffer
This circuit interleaves data symbols within a block before transmission and de-interleaves the received data so that the FEC system is best able to handle short noise bursts or fades.
4.1.9 Frame Sync Detect
This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization pattern that is transmitted to mark the start of every frame.
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 10 of 47
MX919B PRELIMINARY INFORMATION
4.1.10 Rx Input Amp
This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x VDD voltsP-P at the RXAMPOUT pin for a received '...+3 +3 -3 -3 ...' sequence. A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.4), otherwise the DC level of the received signal should be adjusted so that the signal at the modem's RXAMPOUT pin is centered around VBIAS (VDD/2).
4.1.11 RRC Low Pass Filter
This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a 'Root Raised Cosine' frequency response defined by: H( f ) = 1 for 0 < f < 1- b 2T
H( f ) =
( Tf - ) 2 1 sin 1- b b for 2 2 2T 1+ b 2T T= 1 symbol rate
1+ b 2T
H( f ) = 0 for f >
Where
b = 0.2,
This frequency response is illustrated in Figure 5 and Figure 6. In transmit mode, the 4-level symbols are passed through this filter to eliminate the high frequency components which would otherwise cause interference into adjacent radio channels. The input applied to the RRC Tx filter may be impulses or full-width symbols depending on the setting of the Command Register TXIMP bit. See Section 4.7
+3
MX919B
Bit pairs Input Data
+1 -1 -3
binary to symbol
Level Coded Symbols
Transmit filter
Frequency modulator
Modem
Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode
In receive mode, the filter is used to reject HF noise and to equalize the received signal to a form suitable for extracting the 4-level symbols. The equalization characteristics are determined by the setting of the Command Register TXIMP bit.
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Tele: 800 638 5577 336 744 5050
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4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
0 -5 -10
dB -15
-20 -25 -30 0 0.1 0.2 0.3 0.4 0.5
Frequency / Bit Rate
Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5)
0 -5 -10
dB -15
-20 -25 -30 0 0.2 0.4 0.6 0.8 1.0
Frequency / Symbol Rate
Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5) 4.1.12 Tx Output Buffer
This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter. In receive mode, the input of this buffer is connected to VBIAS, unless the RXEYE bit of the Control Register is '1', in which case it is connected to the received signal. When changing from Rx to Tx mode, the input to this buffer will be connected to VBIAS for 8 symbol times while the RRC filter settles. Note: The RC low pass filter formed by the external components R4 and C5 between the TXOUT pin and the input to the radio's frequency modulator forms an important part of the transmit signal filtering. These components may form part of any DC level-shifting and gain adjustment circuitry. The value used for C5 should take into account stray circuit capacitance, and its ground connection should be positioned to give maximum attenuation of high frequency noise into the modulator. The signal at the TXOUT pin is centered around VBIAS. It is approximately 0.2 x VDD voltsP-P for a continuous '+3 +3 -3 -3...' pattern with TXIMP = 0. For typical Tx Eye Diagrams refer to Section 4.7, Figure 17 and Figure 18. For typical Rx Eye Diagrams refer to Section 4.5.4.4, Figure 14. A capacitor may be placed in series with the input to the frequency modulator if AC coupling is desired. See Section 5.4.
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Tele: 800 638 5577 336 744 5050
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Doc. # 20480170.003
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4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
4.1.13 Rx Level/Clock Extraction
These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and measure the received signal amplitude and DC offset. This information is then used to extract the received 4level symbols and also to provide an input to the received Data Quality measuring circuit. The external capacitors C6 and C7 form part of the received signal level measuring circuit. The capacitors C6 and C7 are driven from a very high impedance source so any measurement of the voltages on the DOC pins must be made via high input impedance (MOS input) voltage followers to avoid disturbance of the level measurement circuits. Further details of the level and clock extraction functions are given in Section 5.3.
4.1.14 Clock Oscillator and Dividers
These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a reference frequency which may be generated by the on-chip Xtal oscillator or applied from an external source. Note: If the on-chip Xtal oscillator is to be used, then the external components X1, C3, C4, and R3 are required. If an external clock source is to be used, then it should be connected to the XTAL/CLOCK input pin, the XTAL pin should be left unconnected, and X1, C3, C4, and R3 should not be installed.
4.2 Modem - C Interaction
In general, data is transmitted over-air in the form of messages, or 'Frames', consisting of a 'Frame Preamble' followed by one or more formatted data blocks. The Frame Preamble includes a Frame Synchronization pattern designed to allow the receiving modem to identify the start of a frame. The following data blocks are constructed from the 'raw' data using a combination of CRC (Cyclic Redundancy Checksum) generation, Forward Error Correction coding, and Interleaving. Details of the message formats handled by the modem are provided in Section 4.4, Figure 7, and Figure 8. To reduce the processing load on the associated C, the MX919B modem has been designed to perform as much of the computationally intensive work involved in Frame formatting and de-formatting and (when in receive mode) searching for and synchronizing onto the Frame Preamble. In normal operation, the modem will only require servicing by the C once per received or transmitted block. Therefore, to transmit a block, the controlling C needs only to load the unformatted 'raw' binary data into the modem's Data Block Buffer, then instruct the modem to format and transmit that data. The modem will then calculate and add the CRC bits as required, encode the result as 4-level symbols (with Forward Error Correction coding), and interleave the symbols before transmission. In receive mode, the modem can be instructed to assemble a block's worth of received symbols, de-interleave the symbols, translate them to binary, perform Forward Error Correction, and check the resulting CRC before placing the received binary data into the Data Block Buffer for the C to read. The modem can also handle the transmission and reception of unformatted data using the T4S, T24S, and R4S tasks as described in Sections 4.3 and 4.5.2. These tasks are normally used for the transmission of Symbol and Frame Synchronization sequences. These tasks may also be used for the transmission and reception of special test patterns or special data formats. In such a case, care should be taken to ensure that the transmitted TXOUT signal contains enough level and timing information for the receiving modem's level and clock extraction circuits to function correctly. See Section 5.3.
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Tele: 800 638 5577 336 744 5050
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Doc. # 20480170.003
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4-Level FSK Modem Data Pump
Page 13 of 47
MX919B PRELIMINARY INFORMATION
4.3
Binary to Symbol Translation
Although the over-air signal, and therefore the signals at the modem TXOUT and RXIN pins, consists of 4level symbols, the raw data passing between the modem and the C is in binary form. Translation between binary data and the 4-level symbols is done in one of two ways, depending on the task being performed. 1. Direct way: (simplest form) - converts between 2 binary bits and a single symbol.
SYMBOL +3 +1 -1 -3 MSB 1 1 0 0 LSB 1 0 0 1
Accordingly, 1 byte = 4 symbols = 8 bits, and one byte translates to four symbols for the T4S and R4S tasks and six bytes translates to twenty-four symbols for the T24S task described in Section 4.5.2.
MSB 7 LSB 0
Bits: Symbols:
6
5 b
4
3 c
2
1
a send first
d send last
2. FEC way: (more complicated) - essentially translates groups of 3 binary bits to pairs of 4-level symbols using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB, and RILB described in Section 4.5.2.
(c)2001 MX*COM, INC.
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MX919B PRELIMINARY INFORMATION
4.4
Frame Structure
Figure 7 shows how an over-air message frame may be constructed from a sequence of: a Symbol Sync pattern (preamble), a Frame Sync pattern, and one or more 'Header', 'Intermediate' or 'Last' blocks.
Header Block 76543210 Intermediate Block 76543210 Last Block 76543210
C binary data stored in MX919B data block memory configured as header, intermediate, or last block by MX919B task being executed.
Byte 0 1 2 3 4 5 6 7 8 9 10 11
Data Bytes (10)
Data Bytes (12)
Data Bytes (8)
CRC 1 (2 bytes)
CRC2 (4 bytes)
7
Byte 0
07
Byte 1
0
7 Byte 11
0 '000'
tri-bits
0
1
2
3
4
5
29 30 31 32
FEC Trellis Coding / Decoding (Error Correction)
4-Level Symbols
0 1 2 64 65
Interleaving / De-interleaving
Over-air signal (symbols)
Symbol Sync
Frame Sync 24
'Header' Block 66 66
Intermediate Blocks 66
'Last' Block 66
Frame Preamble Frame
Frame Sync:
-1 +1 -1 +1 -1 3 -3 +3 -3 -1 +1 -3 +3 +3 -1 +1 -3 -3 +1 +3 -1 -3 +1 +3
sent first Symbol Sync: at least 24 symbols of '...+3 +3 -3 -3 ...' sequence
last
Figure 7: Over-Air Signal Format
The 'Header' block is self-contained and includes its own checksum (CRC1). It would normally carry information such as the address of the calling and called parties, the number of following blocks in the frame (if any), and miscellaneous control information. The number of following blocks (if any) is required to allow the Rx device software to expect the Last Block and interpret it as a Last Block rather than an Intermediate Block. There is no other indicator to differentiate a Last Block and an Intermediate Block. The 'Intermediate' block(s) contain only data, the checksum for all of the data in the 'Intermediate' and 'Last' blocks (CRC2) being contained at the end of the 'Last' block. This arrangement, while efficient in terms of data capacity, may not be optimum for poor signal-to-noise conditions, since a reception error in any one of the 'Intermediate' or 'Last' blocks would invalidate the whole frame. In such conditions, increased throughput may be obtained by using the 'Header' block format for all blocks of the frame, so blocks that are received correctly can be identified as such, and do not need to be retransmitted. These, and some other possible frame structures, are shown in Figure 8.
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MX919B PRELIMINARY INFORMATION
A
SYMBOL SYNC SYMBOL SYNC SYMBOL SYNC
FRAME SYNC FRAME SYNC FRAME SYNC
'HEADER' BLOCKS 'LAST' BLOCK
B
'INTERMEDIATE' BLOCKS
C
'INTERMEDIATE' BLOCKS
Figure 8: Alternative Frame Structures
The MX919B performs the entire block formatting and de-formatting required to convert data between C binary form and Over-Air as shown in Figure 7.
4.5 The Programmer's View
To the programmer, the modem appears as 4 write only 8-bit registers, shadowed by 3 read only registers. The individual registers are selected by the A0 and A1 chip inputs:
A1 0 0 1 1 A0 0 1 0 1 Write to Modem Data Buffer Command Register Control Register Mode Register Read from Modem Data Buffer Status Register Data Quality Register Not used
Note: There is a minimum time allowance between accesses of the modem's registers, see Section 6.1.4.
4.5.1 Data Block Buffer
This is a 12-byte read/write buffer used to transfer data (as opposed to command, status, mode, data quality or control information) between the modem and the host C. To the C, the Data Block Buffer appears as a single 8-bit register. The modem ensures that sequential C reads or writes to the buffer are routed to the correct locations within the buffer. The C should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'. The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive mode, the modem will function correctly even if the received data is not read from the Data Buffer by the C.
4.5.2 Command Register
Writing to this register tells the modem to perform a specific task as indicated by the TASK bits and modified by the AQSC, AQLEV, CRC, and TXIMP bits.
Command Register
7
6
5
CRC
4
3
2
1
TASK
0
AQSC AQLEV
TXIMP Reserved Set to '0'
When there is no action to perform, the modem will be in an 'idle' state. If the modem is in transmit mode, the input to the Tx RRC filter will be connected to VBIAS. In receive mode, the modem will continue to measure the received data quality and extract symbols from the received signal, supplying them to the de-interleave buffer, otherwise these received symbols are ignored.
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MX919B PRELIMINARY INFORMATION
4.5.2.1
Command Register B7: AQSC - Acquire Symbol Clock
This bit has no effect in transmit mode. In receive mode, when a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronization is achieved, until it reaches the 'normal' value set by the PLLBW bits of the Control Register. Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be restarted every time a byte written to the Command Register has the AQSC bit set to '1'. The use of the symbol clock acquisition sequence is described in Section 5.3.
4.5.2.2 Command Register B6: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode. In receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is not set to RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond quickly at first, then gradually increasing their response time, therefore improving the measurement accuracy, until the 'normal' value set by the LEVRES bits of the Control Register is reached. Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be restarted every time a byte written to the Command Register has the AQLEV bit set to '1'. The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3.
4.5.2.3 Command Register B5: CRC
This bit allows the user to select between two different initial states of the CRC1 and CRC2 checksum generators. When this bit is set to `0', the CRC generators are initialized to `all ones' as for CCITT X25 CRC calculations. When this bit is set to `1', the CRC generators are initialized to `all zeros'. Setting this bit to `0' provides compatibility with the MX919, a prior member of the MX919 device family. Other systems may set this bit as required. Note: This bit must be set correctly every time the Command Register is written to.
4.5.2.4 Command Register B4: TXIMP - Tx Level/Impulse Shape
This bit allows the user to choose between two transmit symbol waveform shapes as described in Section 4.7. Note: This bit must be set correctly every time the Command Register is written to.
4.5.2.5 4.5.2.6 Command Register B3 - Reserved Command Register B2, B1, B0: TASK
This bit should always be set to '0'. Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are initiated when the C writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL' code. The C should not write a task (other than NULL or RESET) to the Command Register or write to or read from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'. Different tasks apply in receive and transmit modes. When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit data from the Data Buffer, formatting it as required. The C should therefore wait until the BFREE (Buffer Free) bit of the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte number 0 of the block should be written first. Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'. Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave Buffer. Once all of the data has been transferred from the Data Block Buffer, the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the chip IRQ output to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the C that it may write new data and the next task to the modem.
This lets the C write the next task and its associated data to the modem while the modem is still transmitting the data from its previous task.
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MX919B PRELIMINARY INFORMATION
Data from C to Block Buffer Task from C to Command Register BFREE Bit of Status Register IRQ Bit of Status Register IRQ Output (IRQEN = '1') TXOUT Signal
Task 1 data
Task 2 data
from Task 1
from Task 2
Figure 9: Transmit Task Overlapping
When the modem is in receive mode, the C should wait until the BFREE bit of the Status Register is '1', then write the desired task to the Command Register. Once the byte containing the desired task has been written to the Command Register, the modem will: Set the BFREE bit of the Status Register to '0'. Wait until enough received symbols are in the De-interleave Buffer. Decode them as needed and transfer the resulting binary data to the Data Block Buffer Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the IRQ output to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the C that it may read from the Data Block Buffer and write the next task to the modem. If more than 1 byte is contained in the buffer, byte number 0 of the data will be read out first. In this way, the C can read data and write a new task to the modem while the received symbols needed for this new task are being received and stored in the De-interleave Buffer.
RXIN Signal IRQ Output (IRQEN = '1') IRQ Bit of Status Register BFREE Bit of Status Register Task from C to Command Register Data from Block Buffer to C
for Task 1
for Task 2
Task 1
Task 2 Task 1 data
Figure 10: Receive Task Overlapping
Detailed timings for the various tasks are provide in Figure 11 and Figure 12.
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MX919B PRELIMINARY INFORMATION
MX919B Modem Tasks: B2 0 0 0 0 1 1 1 1 4.5.2.7 4.5.2.8 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive Mode Transmit Mode
NULL SFSH RHB RILB SFS R4S NULL RESET
Search for FS + Header Read Header Block Read Intermediate or Last Block Search for Frame sync Read 4 symbols Cancel any current action
NULL T24S THB TIB TLB T4S NULL RESET
Transmit 24 symbols Transmit Header Block Transmit Intermediate Block Transmit Last Block Transmit 4 symbols Cancel any current action
NULL: No effect SFSH: Search for Frame Sync plus Header Block
This 'task' is provided so an AQSC or AQLEV command can be initiated without loading a new task. This task causes the modem to search the received signal for a valid 24-symbol Frame Sync sequence followed by Header Block which has a correct CRC1 checksum. The task continues until a valid Frame Sync plus Header Block has been found. The search consists of two stages: First the modem will attempt to match the incoming symbols against the 24-symbol Frame Synchronization pattern to within the tolerance defined by the FSTOL bits of the Control Register. Once a match has been found, the modem will read in the next 66 symbols as if they were a 'Header' block, decoding the symbols and checking the CRC1 checksum. If this is incorrect, the modem will resume the search, looking for a fresh Frame Sync pattern. If the received CRC1 is correct, the 10 decoded data bytes will be placed into the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1' and the CRCERR bit cleared to '0'. Once detecting that the BFREE bit of the Status Register has gone to '1', the C should read the 10 bytes from the Data Block Buffer and then write the next task to the modem's Command Register.
4.5.2.9 RHB: Read Header Block
This task causes the modem to read the next 66 symbols as a 'Header' Block, decoding them, placing the resulting 10 data bytes and the 2 received CRC1 bytes into the Data Block Buffer, and setting the BFREE and IRQ bits of the Status Register to '1'. When the task is complete, it indicates that the C may read the data from the Data Block Buffer and write the next task to the modem's Command Register. The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1 checksum bytes.
4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block
This task causes the modem to read the next 66 symbols as an 'Intermediate' or 'Last' block (the C should be able to tell from the 'Header' block how many blocks are in the frame and when to expect the 'Last' block). In each case, it will decode the 66 symbols and place the resulting 12 bytes into the Data Block Buffer, setting the BFREE and IRQ bits of the Status Register to '1' when the task is complete. If an 'Intermediate' block is received, then the C should read out all 12 bytes from the Data Block Buffer and ignore the CRCERR bit of the Status Register, for a 'Last' block the C need only read the first 8 bytes from the Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2 checksum.
4.5.2.11 SFS: Search for Frame Sync
This task causes the modem to search the received signal for a 24-symbol sequence which matches the Frame Synchronization pattern to within the tolerance defined by the FSTOL bits of the Mode Register. When a match is found the modem will set the BFREE and IRQ bits of the Status Register to '1' to indicate to the C that it should write the next task to the Command Register.
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MX919B PRELIMINARY INFORMATION
4.5.2.12 R4S: Read 4 Symbols
This task causes the modem to read the next 4 symbols and translate them directly (without de-interleaving or FEC) to an 8-bit byte which is placed into the Data Block Buffer. The BFREE and IRQ bits of the Status Register are then set to '1' to indicate that the C may read the data byte from the Data Block Buffer and write the next task to the Command Register. This task is intended for special tests and channel monitoring - perhaps preceded by a SFS task. Note: It is possible to construct message formats, which do not rely on the block formatting of the THB, TIB, and TLB tasks. This can be accomplished by using T4S or T24S tasks to transmit and R4S to receive the user's data. One should be aware, that the receive level and timing measurement circuits need to see a reasonably 'random' distribution of all four possible symbols in the received signal to operate correctly. Accordingly, binary data may benefit from scrambling before transmission if it is not reasonably 'random' to start with.
4.5.2.13 T24S: Transmit 24 Symbols
This task, which is intended to facilitate the transmission of Symbol and Frame Sync patterns as well as special test sequences, takes 6 bytes of data from the Data Block Buffer and transmits them as 24 4-level symbols without any CRC or FEC. Byte 0 of the Data Block Buffer is sent first, byte 5 last. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1', indicating to the C that it may write the data and command byte for the next task to the modem. The tables below show what data needs to be written to the Data Block Buffer to transmit the MX919B Symbol and Frame Sync sequences:
`Symbol Sync' Symbols Values written to Data Block Buffer Binary Hex Byte 0: 11110101 F5 Byte 1: 11110101 F5 Byte 2: 11110101 F5 Byte 3: 11110101 F5 Byte 4: 11110101 F5 Byte 5: 11110101 F5 Values written to Data Block Buffer Binary Hex Byte 0: 00100010 22 Byte 1: 00110111 37 Byte 2: 01001001 49 Byte 3: 11110010 F2 Byte 4: 01011011 5B Byte 5: 00011011 1B
+3 +3 +3 +3 +3 +3
+3 +3 +3 +3 +3 +3
-3 -3 -3 -3 -3 -3
-3 -3 -3 -3 -3 -3
`Frame Sync' Symbols
-1 -1 -3 +3 -3 -1
+1 +3 -1 +3 -3 -3
-1 -3 +1 -1 +1 +1
+1 +3 -3 +1 +3 +3
4.5.2.14 THB: Transmit Header Block
This task takes 10 bytes of data (Address and Control) from the Data Block Buffer, calculates and appends the 2-byte CRC1 checksum, translates the result to 4-level symbols (with FEC), interleaves the symbols, and transmits the result as a formatted 'Header' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'.
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MX919B PRELIMINARY INFORMATION
4.5.2.15 TIB: Transmit Intermediate Block
This task takes 12 bytes of data from the Data Block Buffer, updates the 4-byte CRC2 checksum for inclusion in the 'Last' block, translates the 12 data bytes to 4-level symbols (with FEC), interleaves the symbols, and transmits the result as a formatted 'Intermediate' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'.
4.5.2.16 TLB: Transmit Last Block
This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CRC2 checksum, translates the resulting 12 bytes to 4-level symbols (with FEC), interleaves the symbols, and transmits the result as a formatted 'Last' Block. Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status Register will be set to '1'.
4.5.2.17 T4S: Transmit 4 Symbols
This command is similar to T24S but takes only one byte from the Data Block Buffer, transmitting it as four 4level symbols.
4.5.2.18 RESET: Stop any current action
This 'task' takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should be used when VDD is applied, to set the modem into a known state. Note: Due to delays in the transmit filter, it will take several symbol times for any change to appear at the TXOUT pin.
4.5.2.19 Task Timing
The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation.
Task Time (symbol times) 1 to 2
t1 t2 t3
Modem Idle state. Time from writing first task to application of first transmit bit to Tx RRC filter. Time from application of first symbol of the task to the Tx RRC filter until BFREE goes to a logic `1'. Time to transmit all symbols of the task. Max time allowed from BFREE going to a logic `1' (high) for next task (and data) to be written to modem.
Any T24S THB/TIB/TLB T4S T24S THB/TIB/TLB T4S T24S THB/TIB/TLB T4S SFS SFSH RHB/RILB R4S SFS SFSH RHB/RILB R4S Any
t4
t5
Time to receive all symbols of task.
t6 t7
Maximum time between first symbol of task entering the de-interleave circuit and the task being written to modem. Maximum time from the last bit of the task entering the de-interleave circuit to BFREE going to a logic `1' (high).
5 16 0 24 66 4 18 49 3 24 (minimum) 90 (minimum) 66 4 21 21 49 3 1
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MX919B PRELIMINARY INFORMATION
Data to Data Block Buffer Task to Command Register IBEMPTY Bit BFREE Bit
1 1 t4
2 2
3 t4 3 t4
t2 t3 t1 Symbols to RRC Filter Modem Tx Output from Task 1
t2
t3
t2
t3
from Task 2
from Task 3
Figure 11: Transmit Task Timing Diagram
Modem Rx Input Symbols to De-Interleave Circuit Data from Data Block Buffer Task to Command Register t6 1 t7 BFREE Bit t6 for Task 1 t5 for Task 2 t5
1
for Task 3 t5
2
3
2 t7
t6
3 t7
Figure 12: Receive Task Timing Diagram 4.5.2.20 RRC Filter Delay
The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times through to the RRC filter in both transmit and receive modes, as illustrated below:
Delay from Tx Input symbol to TXOUT response.
Tx Symbol to RRC Filter
Delay from Rx Input (from FM discriminator) to interpreted data in internal buffer.
Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator
RX Symbol to De-Interleave Buffer
Symbol-times
Figure 13: RRC Low Pass Filter Delay
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MX919B PRELIMINARY INFORMATION
4.5.3
Control Register
This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock extraction, signal level measurement circuits, and the Frame Sync pattern recognition tolerance to inexact matches.
Control Register
7
6
5
4
3
2
1
0
CKDIV
FSTOL
LEVRES
PLLBW
4.5.3.1
Control Register B7, B6: CKDIV - Clock Division Ratio
These bits control a frequency divider driven from the clock signal present at the XTAL pin, therefore determining the nominal symbol rate. Because each symbol represents two bits, bit rates are 2x the symbol rates. The table below shows how symbol rates of 2400/4800/9600 symbols/sec (4800/9600/19200bps) may be obtained from common Xtal frequencies:
Xtal Frequency (MHz) 2.4576 4.9152 9.8304 Symbol Rate (symbols/sec) / Bit Rate (bps) 4800/9600 9600/19200 2400/4800 4800/9600 9600/19200 2400/4800 4800/9600 2400/4800
B7
B6
0 0 1 1
4.5.3.2
0 1 0 1
Division Ratio: Xtal Frequency/Symbol Rate 512 1024 2048 4096
Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches
These two bits have no effect in transmit mode. In receive mode, they define the maximum number of mismatches allowed during a search for the Frame Sync pattern:
B5 0 0 1 1 B4 0 1 0 1 Mismatches allowed 0 2 4 6
Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol '+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received symbol value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for normal use.
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MX919B PRELIMINARY INFORMATION
4.5.3.3
Control Register B3, B2: LEVRES - Level Measurement Modes
These two bits have no effect in transmit mode. In receive mode they set the 'normal' or 'steady state' operating mode of the Rx signal amplitude and DC offset measuring and tracking circuits. These circuits analyze the Rx signal envelope and charge the DOC1 and DOC2 capacitors to 'store' signal maximum and minimum references that are used in the data reception process. This setting is temporarily overridden during the automatic sequencing triggered by an AQLEV command when level is initially being acquired as described in Section 5.3.
B3 0 0 1 1 B2 0 1 0 1 Mode
Hold Level Track Lossy Peak Detect Slow Peak Detect
In normal use the LEVRES bits should be set to '0 1' (Level Track). The other modes are intended for special purposes, for device testing, or are invoked automatically during an AQLEV sequence. In 'Slow Peak Detect' modes, the positive and negative excursions of the received signal (after filtering) are measured by peak rectifiers driving the DOC1 and DOC2 capacitors to establish the amplitude of the signal and any DC offset with regards to VBIAS. This mode provides good overall performance, particularly when acquiring level information at the start of a received message, but does not work as well with certain long sequences of repeated data byte values. It is also susceptible to large amplitude noise spikes, which can be caused by deep fades. The 'Lossy Peak Detect' mode is similar to 'Slow Peak Detect' but the capacitor discharge time constant is much shorter so this mode is not suitable for normal data reception and is only used within part of the automatic AQLEV acquisition sequence. In 'Level Track' mode the DOC capacitor voltages are slowly adjusted by the MX919B in such a way as to minimize the average errors seen in the received signal. This mode provides the best overall performance, being much more accurate than 'Slow Peak Detect' when receiving large amplitude noise spikes on long sequences of repeated data byte values. It does, however, depend on the measured levels and timing being approximately correct. If either of these is significantly wrong then the correction algorithm used by the 'Level Track' mode can actually drive the voltages on the DOC capacitors away from their optimum levels. For this reason, the automatic AQLEV acquisition sequence (see Section 5.3) forces the level measuring circuits into 'Slow Peak Detect' mode until a Frame Sync pattern has been found.
4.5.3.4 Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes
These two bits have no effect in transmit mode. In receive mode, they set the 'normal' or 'steady state' bandwidth of the Rx clock extraction Phase Locked Loop circuit. The PLL circuit synchronizes itself with the Rx Signal to develop a local clock signal used in the data clock recovery process. This setting will be temporarily overridden during the automatic sequencing of an AQSC command when Rx clock extraction circuits are initially being trained as described in Section 5.3.
B1 0 0 1 1 B0 0 1 0 1 PLL Mode
Hold Level Track Lossy Peak Detect Slow Peak Detect
The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the frequency of the receiving modem's crystal are both within 100ppm of nominal, except at the start of a symbol clock acquisition sequence (AQSC) when 'Wide Bandwidth' should be selected as described in Section 5.3 If the received symbol rate and the crystal frequency are both within 20ppm of nominal then selection of the 'Narrow Bandwidth' setting will provide better performance especially through fades or noise bursts which may otherwise pull the PLL away from its optimum timing. In this case however; it is recommended that the PLLBW bits only be set to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth' mode for about 200 symbol times to ensure accurate lock has first been achieved.
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MX919B PRELIMINARY INFORMATION
The 'Hold' setting disables the feedback loop of the PLL which continues to run at a rate determined only by the actual crystal frequency and the setting of the Control Register CKDIV bits, not the PLL's operating frequency immediately prior to the 'Hold' setting.
4.5.4 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register
7
6
5
4
3
2
1
Set to '000'
0
IRQEN INVSYM Tx/Rx
RXEYE PSAVE
4.5.4.1
Mode Register B7: IRQEN - IRQ Output Enable
When this bit is set to '1', the IRQ chip output pin is pulled low (VSS) given the IRQ bit of the Status Register is a '1'.
4.5.4.2 Mode Register B6: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
B6 Symbol +3 -3 Signal at TXOUT Above VBIAS Below VBIAS Signal at RXAMPOUT Below VBIAS Above VBIAS
0
1
+3 -3
Below VBIAS Above VBIAS
Above VBIAS Below VBIAS
Note: B6 must be normally set to the same value in Tx and Rx devices for successful operation.
4.5.4.3 Mode Register B5: TX/RX - Tx/Rx Mode
Setting this bit to '1' places the modem into the Transmit mode, clearing it to '0' puts the modem into the Receive mode. Note: Changing between receive and transmit modes will cancel any current task.
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MX919B PRELIMINARY INFORMATION
4.5.4.4
Mode Register B4: RXEYE - Show Rx Eye
This bit should normally be set to '0'. Setting it to '1' when the modem is in receive mode configures the modem for a special test mode, in which the input of the Tx output buffer is connected to the Rx Symbol/Clock extraction circuit at a point which carries the equalized receive signal. This may be monitored with an oscilloscope (at the TXOUT pin itself), to assess the quality of the complete radio channel including the Tx and Rx modem filters, the Tx modulator and the Rx IF filters, and FM demodulator. This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered signal (before Rx equalization) is not very recognizable so it is generally not useful. The resulting eye diagram (for reasonably random data) should ideally be as shown in the following Figure 14, with 4 distinct and equally spaced level crossing points.
Figure 14: Ideal 'RXEYE' Signal Note:
A two-channel oscilloscope is needed for this testing. One channel of the oscilloscope should be placed on the signal path of interest, such as the Tx output. If the Rx eye diagram is to be viewed, set the "RXEYE" bit in the Mode Register to "1" and connect the oscilloscope probe downstream of the external RC filter on the TXOUT pin. (This Mode Register bit causes the MX919B to enter a special test mode whereby the Rx output is placed on the TXOUT pin. This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered signal is not very recognizable and is generally not useful.) The other oscilloscope channel should be used for triggering and should ideally be placed on the transmitting MX919B IRQ pin. This will allow the triggering to be synchronized with the completion of each transmitted data word. If this triggering location is not practical, use the receiving MX919B IRQ signal for triggering. The falling edge of the IRQ line should be used for triggering. The data stream used for this testing should have a reasonably random structure.
4.5.4.5
Mode Register B3: PSAVE - Powersave
When this bit is a `1', the modem will be in a `powersave' mode in which the internal filters, the Rx Symbol and Clock extraction circuits, and the Tx output buffer will be disabled. The TXOUT pin will be connected to VBIAS through a high value internal resistance. The Xtal clock oscillator, Rx input amplifier and the C interface logic will continue to operate. Setting the PSAVE bit to `0' restores power to all of the chip circuitry. Note: The internal filters, and therefore the TXOUT pin in transmit mode, will take approximately 20 symboltimes to settle after the PSAVE bit has gone from `1' to `0'.
4.5.4.6 Mode Register B2, B1, B0
These bits should be set to '000'.
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MX919B PRELIMINARY INFORMATION
4.5.5
Status Register
This register may be read by the C to determine the current state of the modem.
Status Register
7
IRQ
6
BFREE
5
4
3
2
1
Reserved
0
DIBOVF IBEMPTY CRCERR
4.5.5.1
Status Register B7: IRQ - Interrupt Request
This bit is set to '1' by: The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a change to the Mode Register TX /RX or PSAVE bits
or or
The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by changing the Mode Register TX /RX or PSAVE bits. The Status Register DIBOVF bit going from '0' to '1'.
The IRQ bit is cleared to '0' immediately after a read of the Status Register. If the IRQEN bit of the Mode Register is '1', then the chip IRQ output will be pulled low (VSS) when the IRQ bit is set to '1', and will go high impedance when the Status Register is read.
4.5.5.2 Status Register B6: BFREE - Data Block Buffer Free
This bit reflects the availability of the Data Block Buffer and is cleared to '0' when a task other than NULL or RESET is written to the Command Register. In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem when the modem is ready for the C to write new data to the Data Block Buffer and the next task to the Command Register. In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem when it has completed a task and any data associated with that task has been placed into the Data Block Buffer. The C may then read that data and write the next task to the Command Register. The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register TX /RX or PSAVE bits are changed.
4.5.5.3 Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a gap in the transmit output signal. The bit is also set to '1' by a RESET task or by a change of the Mode Register TX /RX or PSAVE bits, but in these cases the IRQ bit will not be set. The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the Command Register. Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level (halfway between '+1' and '-1') signal will be sent to the RRC filter. In receive mode this bit will be '0'.
4.5.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB or R4S task is written to the Command Register too late to allow continuous reception. The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the Command Register or by changing the TX /RX or PSAVE bits of the Mode Register. In transmit mode this bit will be '0'.
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MX919B PRELIMINARY INFORMATION
4.5.5.5
Status Register B3: CRCERR - CRC Checksum Error
In receive mode, this bit will be updated at the end of a SFSH, RHB or RILB task to reflect the result of the receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error. Note: This bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is received. The bit is cleared to '0' by a RESET task or by changing the TX /RX , or PSAVE bits of the Mode Register. In transmit mode this bit is '0'.
4.5.5.6 4.5.6 Status Register B2, B1, B0 Data Quality Register
These bits are reserved for future use. In receive mode, the MX919B continually measures the 'quality' of the received signal, by comparing the actual received waveform over the previous 64 symbol times against an internally generated 'ideal' 4-level FSK baseband signal. The result is placed into bits 3-7 of the Data Quality Register for the C to read at any time, bits 0-2 being always set to '0'. Figure 15 shows how the value (0-255) read from the Data Quality Register varies with received signal-to-noise ratio:
250 200
150 DQ 100 50 0 5 7 9 11 13 S/N dB (noise in 2 x symbol-rate bandwidth) 15
Figure 15: Typical Data Quality Reading vs S/N
The Data Quality readings are only valid when the modem has successfully acquired signal level and timing lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when the LEVRES setting is 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set to 'Wide' or if the received signal waveform is distorted in any significant way. Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system performance in some applications.
4.6 4.6.1 4.6.1.1 CRC, FEC, and Interleaving Cyclic Redundancy Codes CRC1
This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block, which provides error detection coverage for the Header Block of a message. It is calculated by the modem from the first 80 bits of the Header Block (Bytes 0 to 9 inclusive) using the generator polynomial: x16 + x12 + x5 + 1
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MX919B PRELIMINARY INFORMATION
4.6.1.2
CRC2
This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the 'Last' Block, which provides error detection coverage for the combined Intermediate Blocks and Last Block of a message. It is calculated by the modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block using the generator polynomial: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 Note: In receive mode the CRC2 checksum circuits are initialized on completion of any task other than NULL or RILB. In transmit mode the CRC2 checksum circuits are initialized on completion of any task other than NULL, TIB, or TLB. Command Register bit B5 (CRC) allows the user to select between two different forms of the CRC1 and CRC2 checksums. When this bit is set to '0', the CRC generators are initialized to 'all ones' for calculations such as CCITT X25 CRC. When this bit is set to '1', the CRC generators are initialized to 'all zeros'.
4.6.1.3 Forward Error Correction
In transmit mode, the MX919B uses a Trellis Encoder to translate the 96 bits (12 bytes) of a 'Header', 'Intermediate' or 'Last' Block into a 66-symbol (132 bits) sequence which includes FEC information. In receive mode, the MX919B decodes the received 66 symbols of a block into 96 bits of binary data using a 'Soft Decision' Viterbi algorithm to perform decoding and error correction.
4.6.1.4 Interleaving
The 66 symbols of a 'Header', 'Intermediate' or 'Last' block are interleaved by the modem before transmission to provide protection against the effects of noise bursts and short fades. In receive mode, the MX919B de-interleaves the received symbols prior to decoding.
4.7 Transmitted Symbol Shape
Bit 4 of the Command Register (TXIMP) selects the transmit baseband signal and the receive signal equalization as follows: If the TXIMP bit is '0', then the transmit baseband signal is generated by feeding full-symbol-time-width 4-level symbols into the RRC lowpass filter. The receive signal equalization is optimized for this type of signal. With this setting, the MX919B is compatible with the MX919A devices, another member of the MX919 device family. If the TXIMP bit is set to '1,' impulses, rather than full-symbol-time-width symbols are fed into the RRC filter when in TX mode, and the receive signal equalization is suitably adjusted in RX mode.
TXIMP = 0 +3 +1 -1 -3 1 symbol time +3 +1 -1 -3 1 symbol time TXIMP = 1
Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1
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MX919B PRELIMINARY INFORMATION
Figure 17: Tx Signal Eye TXIMP = 0
Figure 18: Tx Signal Eye TXIMP = 1
Note: Setting TXIMP to '1' affects the Tx output signal level as shown in Section 6.1.3 and the table below.
TXIMP = 0 0.157VDD TXIMP = 1 0.157VDD
Nominal Voltage difference between continuous `+3' and continuous `-3' symbol outputs Nominal VP-P for continuous `+3+3-3-3...' symbol pattern.
0.20VDD
0.22VDD
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MX919B PRELIMINARY INFORMATION
5. Application
5.1 Transmit Frame Example
The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are provided below: 1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQEN and TX/RX bits of the Mode Register are '1', the RXEYE and PSAVE bits are '0', and the INVSYM bit is set appropriately. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes (a preamble) to the Data Block Buffer and a T24S task to the Command Register. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. Write 6 byte Frame Sync to the Data Block Buffer and a T24S task to the Command Register. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'.
2. 3. 4. 5. 6. 7. 8. 9.
10. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 12. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits should be '1'. Note: The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass completely through the RRC filter. Figure 19 and Figure 20 illustrate the host C routines needed to send a single Frame consisting of Symbol and Frame Sync patterns, a Header block, and any number of Intermediate blocks and one Last Block. It is assumed that the Tx Interrupt Service Routine Figure 20 is called when the MX919B IRQ output line goes low.
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MX919B PRELIMINARY INFORMATION
START
Ensure that the Control Register has been loaded with a suitable CKDIV value
Set C variable 'IBLOCKS' to the number of Intermediate blocks to be transmitted
Ensure that the Mode Register IRQEN, PSAVE and RXEYE bits are '0', the TX/RX bit is '1', and the INVSYM bit is set appropriately
Set C variable 'STATE' to 0
Set the Mode Register IRQEN bit to '1' Write a RESET task to the Command Register Enable C's MX919B Tx Interrupt Service Routine Read the Status Register Write 6 bytes of Symbol Sync pattern to the Data Buffer BFREE bit = 1 ? Yes Write a T24S task to the Command Register No Note: during this time the C may perform other functions, as the C variable 'STATE' is updated by the interrupt service routine
Yes
'STATE' < 5 ?
No Disable C's MX919B Tx Interrupt Service Routine
Set the Mode Register IRQEN bit to '0'
No
'STATE' = 5 ?
Yes END with error END
Figure 19: Transmit Frame Example Flowchart, Main Program
Notes 1. The RESET command in Figure 19 and the practice of disabling the MX919B's IRQ output when not needed are not essential but can eliminate problems during debugging and if errors occur in operation 2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command Register.
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MX919B PRELIMINARY INFORMATION
START
( IRQ line goes low )
Read Status Register
RETURN
( Not MX919B IRQ )
No
IRQ bit = 1 ?
Value of C variable 'STATE' on entry to IRQ routine and corresponding MX919B's actions: 0: Symbol Sync pattern being transmitted, load Frame Sync pattern & T24S task. 1: Frame Sync pattern being transmitted, load Header Block bytes and THB task. 2: Header or Intermmediate Block being transmitted, load Intermediate or Last Block bytes & TIB or TLB task. 3: Last block being transmitted, . ignore this interrupt. 4: Waiting for end of transmission, finish on interrupt with IBEMPTY bit set.
Yes No
E
BFREE bit = 1 ?
Yes Yes
'STATE' = 4 ?
No Yes
E
No
IBEMPTY bit = 1 ?
Yes
E
IBEMPTY bit = 1 ?
No
E
'STATE' = 0 ?
Yes
Write 6 byte Frame Sync pattern to the Data Buffer then write a T24S task to the Command Register
Set C variable 'STATE' to 9
No Yes Write 10 Header Block data bytes to the Data Buffer then write a THB task to the Command Register
'STATE' = 1 ?
RETURN
( Error ) No No
'STATE' = 2 ?
Yes
E
No
'STATE' = 3 ?
Yes
Write 12 Intermediate Block data bytes to the Data Buffer then write a TIB task to the Command Register
No
'IBLOCKS' = 0 ?
Yes
Write 8 Last Block data bytes to the Data Buffer then write a TLB task to the Command Register
Decrement C variable 'IBLOCKS'
Increment C variable 'STATE'
RETURN
RETURN
Figure 20: Tx Interrupt Service Routine
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MX919B PRELIMINARY INFORMATION
5.2
Receive Frame Example
The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences and one each Header, Intermediate and Last blocks are shown below; 1. Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW values, and that the IRQEN bit of the Mode Register is '1', the TX /RX PSAVE, and RXEYE bits are '0', and the INVSYM bit is set appropriately. Wait until the received carrier has been present for at least 8 symbol times (see Section 5.3). Read the Status Register to ensure that the BFREE bit is '1'. Write a byte containing a SFSH task and with the AQSC and AQLEV bits set to '1' to the Command Register. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the CRCERR and DIBOVF bits should be '0'. Check that the CRCERR bit of the Status Register is '0' and read 10 Header Block bytes from the Data Block Buffer. Write a RILB task to the Command Register. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the DIBOVF bit '0'. Read 12 Intermediate Block bytes from the Data Block Buffer.
2. 3. 4. 5. 6. 7. 8. 9.
10. Write a RILB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the DIBOVF bit '0'. 12. Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from Data Buffer. Figure 21 and Figure 22 illustrate the host C routines needed to receive a single Frame consisting of Symbol and Frame Sync patterns, a Header Block, any number of Intermediate blocks and one Last block. It is assumed that the Rx Interrupt Service Routine Figure 22 is called when the MX919B's IRQ output goes low.
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MX919B PRELIMINARY INFORMATION
START
Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW values Wait until the received carrier has been present for at least 8 symbol times
Ensure that the Mode Register IRQEN, PSAVE, RXEYE and TX/RX bits are '0', and the INVSYM bit is set appropriately
Set C variable 'STATE' to 0 Write a RESET task to the Command Register Set the Mode Register IRQEN bit to '1' Read the Status Register Enable C's MX919B Rx Interrupt Service Routine Yes Write a SFSH task to the Command Register with the AQSC and AQLEV bits set to '1'
BFREE bit = 1 ?
No Note: during this time the C may perform other functions, as the C variable 'STATE' is updated by the interrupt service routine
Yes
'STATE' < 3 ?
No Disable C's MX919B Rx Interrupt Service Routine
Set the Mode Register IRQEN bit to '0'
No
'STATE' = 3 ?
Yes END with error END
Figure 21: Receive Frame Example Flowchart, Main Program
Notes 1. The RESET command in Figure 21 and the practice of disabling the MX919B's IRQ output when not needed are not essential but can eliminate problems during debugging and if errors occur in operation. 2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command Register.
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MX919B PRELIMINARY INFORMATION
START
( IRQ line goes low )
Value of C variable 'STATE' on entry to IRQ routine and corresponding MX919B's actions: 0 : Frame Sync has been recognized and Header block received, read out data and load RILB task. 1 : Intermediate block has been received, read out data and load RILB task.
Read Status Register
IRQ bit = 1 ?
No
RETURN
( Not MX919B IRQ )
2 : Last block has been received, read out data and finish.
Yes No
BFREE bit = 1 ?
Yes No
E
DIBOVF bit = 0 ?
Yes No
E
'STATE' = 1 ?
Yes CRCERR bit = 0 ?
No
Yes Yes
E
'STATE' = 0 ?
Read 12 Intermediate Block bytes from the Data Buffer then write a RILB task to the Command Register
Read 10 Header block bytes from the Data Buffer then write a RILB task to the Command Register SEE NOTE BELOW
No
Decrement C variable 'IBLOCKS'
Set C variable 'IBLOCKS' to the number of Intermediate Blocks to be received No 'STATE' = 2 ? Yes
No
'IBLOCKS' = 0 ?
E
Read 8 Last Block data bytes from the Data Buffer.
Yes Set C variable 'STATE' to 2 Set C variable 'STATE' to 9 Increment C variable 'STATE'
RETURN
RETURN
( Error )
RETURN
Figure 22: Rx Interrupt Service routine
Note: This routine assumes that the number of Intermediate blocks in the Frame is contained within the Header Block Data.
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MX919B PRELIMINARY INFORMATION
5.3 5.3.1
Clock Extraction and Level Measurement Systems Supported Types of Systems
The MX919B is intended for use in systems where: 1. The Symbol Sync pattern is transmitted immediately on start-up of the transmitter, before the first Frame Sync pattern (see Figure 23). 2. A terminal may remain powered up indefinitely, transmitting concatenated Frames with or without intervening Symbol Sync patterns (each Frame having a Frame Sync pattern and symbol timing being maintained from one Frame to the next). 3. A receiving modem may be switched onto a channel before the distant transmitter has started up, or may be switched onto a channel where the transmitting station is already sending concatenated Frames
5.3.2 Clock and Level Acquisition Procedures with RF Carrier Detect
When the receiving modem is enabled or switched onto a channel, it needs to establish the received symbol levels, clock timing, and look for a Frame Sync pattern in the incoming signal. This is best done by the following procedure: 1. Ensure that the Control Register's PLLBW bits are set to 'Wide' and the LEVRES bits to 'Track'. 2. Wait until a received carrier has been present for 8 symbol times. This 8-symbol delay gives time for the received signal to propagate through the modem's RRC filter. An 'RF received 8 symbol times' qualifying function can be included in a radio's carrier detect circuitry to take this into account. 3. Write a SFS or SFSH task to the Command Register with the AQSC and the AQLEV bits set to '1'. 4. When the modem interrupts to signal that it has recognized a Frame Sync pattern (or completed the SFSH task) then change the PLLBW bits to 'Medium'. Once the receiving modem has achieved level and symbol timing synchronization with a particular channel as evidenced by recognition of a Frame Sync pattern - then subsequent concatenated Frames can be read by simply issuing SFS or SFSH tasks at appropriate times, keeping the ASQSC and AQLEV bits at zero, and the PLLBW and LEVRES bits at their current 'Medium' and 'Track' settings, respectively.
Noise Symbol Sync Frame Sync Rest of Frame
Rx Signal from FM discriminator to Modem 8-Symbol delay determined by external circuit such as RF carrier detect Set AQSC and AQLEV bits to start Acquisition sequences Level Measurement and Clock Extraction Circuits Increasing accuracy and lengthening response times
Figure 23: Acquisition Sequence Timing 5.3.3 Clock and Level Acquisition Procedure without RF Carrier Detect
It is also possible to use the modem in a system where there is an indeterminate delay between the RF transmitter turn on time and the transmission moment of the Symbol Sync pattern, or where a receive carrier detect signal is not available to the controlling C, or where the transmitting terminal can send separate unsynchronized Frames. In these cases, each Frame should be preceded by, a Symbol Sync pattern which should be extended to about 100 symbols and the procedure provided in Section 5.3.2. used.
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MX919B PRELIMINARY INFORMATION
5.3.4
Automatic Acquisition Functions
Setting the AQSC and AQLEV bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude, and DC offset as quickly as possible before switching to accurate - but slower - measurement modes. These acquisition sequences act very quickly if triggered at the start of a received Symbol Sync pattern (as shown in Figure 23), but will still function correctly, although more slowly, if started any time during a normal Frame as when the receiver is switched onto a channel where the transmitter is operating continuously. The automatic AQLEV Level Measurement acquisition sequence starts with the level measurement circuits being put into 'Clamp' Mode for one symbol time to quickly set the voltages on the DOC pins to approximately correct levels. The level measurement circuits are then automatically set to 'Lossy Peak Detect' mode for 15 symbol times, then 'Slow Peak Detect' until a received Frame Sync pattern is recognized, after which the automatic sequence ends and the level measurement circuit mode reverts to the mode set by the LEVRES bits of the Control Register (normally 'Level Track'). The peak detectors used in both 'Slow' and 'Lossy Peak Detect' modes include additional low pass filtering of the received signal which greatly reduces the effect of pattern noise on the reference voltages held on the external DOC capacitors, but means that pairs of '+3' (and '-3') symbols need to be received to establish the correct levels. Two pairs of '+3' and two pairs of '-3' symbols received after the start of an AQLEV sequence are sufficient to correctly set the levels on the DOC capacitors. The automatic AQSC Symbol Clock acquisition sequence sets the PLL to 'Extra Wide Bandwidth' mode for 16 symbol times (this mode is not one of those which can be selected by the Control Register PLLBW bits) then changes to 'Wide' bandwidth. After 45 symbol times, the PLL mode will revert to that set by the Control Register PLLBW bits.
5.4 AC Coupling
For a practical circuit, ac coupling between the modem's transmit output to the frequency modulator and between the receiver's frequency discriminator and the receive input of the modem may be desired. There are, however, two issues which deserve consideration: 1. AC coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph illustrates the typical bit error rates at 4800 symbols/sec (9600bps) without FEC for reasonably random data with differing degrees of AC coupling:
1.E-01
1.E-02
(c)2001 MX*COM, INC.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
BER
1.E-03 Tx & Rx DC coupled Tx 5Hz, RxDC Tx 5Hz, Rx5Hz Tx 5Hz, Rx10Hz 1.E-04 4 5 6 7 8 9 10 11 12 13 14 S/N dB (Noise in 20 to 9600Hz band)
Figure 24: Effect of AC Coupling on BER (without FEC)
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MX919B PRELIMINARY INFORMATION
2. Any ac coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 25 below, the time for this step to decay to 37% of its original value is 'RC' where:
RC = 1 2(3dB cut - off frequency of the RC network)
which is 32ms, or 153 symbol times at 4800 symbols/sec (9600bps) for a 5Hz network.
Step Input to RC Circuit
100% Output of RC Circuit 37% T = RC
Figure 25: Decay Time - AC Coupling
In general, it is best to DC couple the receiver discriminator to the modem and ensure that any AC coupling to the transmitter's frequency modulator has a -3dB cut-off frequency of no higher than 5Hz for 4800 symbols/sec (9600bps).
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
5.5
Radio Performance
The maximum data rate that can be transmitted over a radio channel using these modems depends on: * RF channel spacing. * Allowable adjacent channel interference. * Symbol rate. * Peak carrier deviation (modulation index). * Tx and Rx reference oscillator accuracy. * Modulator and demodulator linearity. * Receiver IF filter frequency and phase characteristics. * Use of error correction techniques. * Acceptable error rate. As a guide, 4800 symbols/sec (9600bps) can be achieved (subject to local regulatory requirements) over a system with 12.5kHz channel spacing if the transmitter frequency deviation is set to 2.5kHz peak for a repetitive ' +3 +3 -3 -3 ... ' pattern and the maximum difference between transmitter and receiver 'carrier' frequencies is less than 2400Hz. The modulation scheme employed by these modems is designed to achieve high data throughput by exploiting as much as possible of the RF channel bandwidth. However; this does place constraints on the performance of the radio. Particular attention must be paid to: * Linearity, frequency, and phase response of the Tx Frequency Modulator. For a 4800 symbols/sec (9600bps) system, the frequency response should be within 2dB over the range 3Hz to 5kHz, relative to 2400Hz. * The bandwidth and phase response of the receiver's IF filters. * Accuracy of the Tx and Rx reference oscillators, as any difference will shift the received signal towards the skirts of the IF filter response and cause a DC offset at the discriminator output. Viewing the equalized received signal eye diagram, using the Mode Register RXEYE function, provides a good indication of the overall RF transmitter/receiver performance.
Rx FREQUENCY DISCRIMINATOR SIGNAL LEVEL ADJUSTMENT DC LEVEL ADJUSTMENT RXIN RXAMPOUT Rx CIRCUITS D0 - D7 A0 - A1 CS RD WR IRQ Tx CIRCUITS TXOUT
Tx FREQUENCY MODULATOR
SIGNAL AND DC LEVEL ADJUSTMENT
C C
D0 - D7 A0 - A1 CS RD WR IRQ
MX919B MODEM
Figure 26: Typical Connections between Radio and MX919B
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
5.6
Received Signal Quality Monitor
In applications where the modem has to monitor a long transmission containing a number of concatenated Frames, it is recommended that the controlling software include a function which regularly checks that the modem is still receiving a good data signal and triggers a re-acquisition and possibly changes to another channel if a problem is encountered. This strategy has been shown to improve the system's overall performance in situation where fading, large noise bursts, severe co-channel interference, or loss of the received signal for long periods are likely to occur. Such a function can be simply implemented by regularly reading the Data Quality Register, which gives a measure of the overall quality of the received signal, as well as the current effectiveness of the modem's clock extraction and level measurement systems. Experience has shown that if two consecutive DQ readings are both less than 50 then it is worth instructing the MX919B to re-acquire the received signal levels and timing once it has been established that the received carrier level is satisfactory. Re-acquisition should follow the procedure given in Section 5.3. The intervals between Data Quality readings is not critical, but should be a minimum of 64 symbol times except for the first reading made after triggering the AQSC and AQLEV automatic acquisition sequences, which should be delayed for about 250 symbol times. A suitable algorithm is shown in Figure 27.
AQSC/AQLEV task issued
Reset timer. Set C variable 'LAST_DQ' to 99
No
Timer > 250 ?
Note: Times are symbol times.
Read DQ register into C variable 'THIS_DQ'
'THIS_DQ' < 50 ? Yes 'LAST_DQ' < 50 ? Yes
No
No Copy 'THIS_DQ' to 'LAST DQ'. Reset Timer.
Re Acquire
No
Timer > 64 ?
Yes
Figure 27: Received Signal Quality Monitor Flowchart
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
6. Performance Specification
6.1 6.1.1 Electrical Performance Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
General Min. -0.3 -0.3 Max. 7.0 VDD + 0.3 Units V V
Supply (VDD - VSS) Voltage on any pin to VSS Current VDD VSS Any other pin DW, LH, P Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature DS Package Total Allowable Power Dissipation at TAMB = 25C Derating above 25C Storage Temperature Operating Temperature
6.1.2 Operating Limits
-30 -30 -20
30 30 20 800 13 125 85 550 9 125 85
mA mA mA mW mW/C above 25C C C mW mW/C above 25C C C
-55 -40
-55 -40
Correct operation of the device outside these limits is not implied.
Notes Min. 3.0 2400 -40 1.0 Max. 5.5 9600 85 10.0 Units V Symbols/sec C MHz
Supply (VDD - VSS) Symbol Rate Temperature Xtal Frequency
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
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MX919B PRELIMINARY INFORMATION
6.1.3
Operating Characteristics
For the following conditions unless otherwise specified: Xtal Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec, Noise Bandwidth = 0 to 9600Hz, VDD = 5.0V @ TAMB = 25C
Notes DC Parameters IDD IDD (VDD = 3.3V) IDD (Powersave Mode) IDD (Powersave Mode, VDD = 3.3V) AC Parameters TX Output TXOUT Impedance Min. Typ. Max. Units
1 1 1 1
4.0 2.5 1.5 0.6
10.0 6.3
mA mA mA mA
2 3 3 4 0.8 0.88 -0.25
1.0 1.0 1.1
2.5 1.2 1.32 0.25
k VP-P VP-P V M V/V VP-P V ns ns M dB VDD VDD A pF VDD VDD A
Signal Level TXIMP = 0 TXIMP = 1 Output DC Offset with respect to VDD/2 RX Input RXIN Impedance (at 100Hz) RXIN Amp Voltage Gain (input = 1mVRMS at 100Hz) Input Signal Level DC Offset with respect to VDD/2 XTAL/CLOCK INPUT `High' Pulse Width `Low' Pulse Width Input Impedance (at 100Hz) Inverter Gain (input = 1mVRMS at 100Hz) C Interface Input Logic `1' Level Input Logic `0' Level Input Leakage Current (VIN = 0 to VDD) Input Capacitance Output Logic `1' Level (IOH = 120A) Output Logic `0' Level (IOL = 360A) `Off' State Leakage Current (VOUT = VDD)
10.0 5 5 6 6 0.7 -0.5 40 40 10.0 20 7,8 7,8 7,8 7,8 8 8,9 9 70% -5.0 10.0 92% 8% 10 30% 5.0 300 1.0 1.3 0.5
6.1.3.1 Operating Characteristics Notes: 1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator. 2. Small signal impedance. 3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence, (Tx output level is proportional to VDD). 4. Measured at the TXOUT pin with the modem in the Tx idle mode. 5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence, TXIMP = 0 or 1, The optimum level and DC offset values are proportional to VDD. 6. Timing for an external input to the XTAL/CLOCK pin.
7. WR , RD , CS , A0 and A1 pins. 8. D0 - D7 pins. 9. IRQ pin.
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4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
6.1.4
Timing Notes Min. 0 Typ. Max. Units ns
C Parallel Interface Timings (see Figure 28 ) tACSL Address valid to CS low time
tAH tCSH tCSHI tCSRWL tDHR tDHW tDSW tRHCSL tRACL tRARL tRL tRX tWHCSL tWL
Address hold time CS hold time CS high time CS to WR or RD low time Read data hold time Write data hold time Write data setup time RD high to CS low time (write) Read access time from CS low Read access time from RD low RD low time RD high to D0-D7 3 state time WR high to CS low time (read) WR low time 2 2 1
0 0 6 0 0 0 90 0 175 145 200 50 0 200
ns ns clock cycles ns ns ns ns ns ns ns ns ns ns ns
Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin. 2. With 30pF max to VSS on D0 - D7 pins.
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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All trademarks and service marks are held by their respective companies.
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MX919B PRELIMINARY INFORMATION
WRITE CYCLE (DATA TO MODEM) ADDRESS A0, A1 tACSL CS tWL WR tRHCSL RD tCSRWL
tAH ADDRESS VALID tCSH tCSHI
tDSW tDHW
DATA D0 to D7 (1 byte)
DATA VALID
READ CYCLE (DATA FROM MODEM) tAH ADDRESS A0, A1 tACSL CS tWHCSL tCSHI ADDRESS VALID tCSH
WR
tCSRWL tRL
RD tRARL DATA D0 to D7 (1 byte) tDHR DATA VALID tRACL
tRX
Figure 28: C Parallel Interface Timings
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
6.1.5
Typical Bit Error Rate
1E-1 BER with FEC 1E-2 BER without FEC
1E-3 BER 1E-4
1E-5
1E-6 8 9 10 11 12 13 14 15 16 S/N dB (Noise in 2 x Symbol RateBandwidth)
Figure 29: Typical Bit Error Rate With and Without FEC
Measured under nominal working conditions, LEVRES bits set to 'Level Track' or 'Slow Peak Detect' and PLLBW bits set to 'Medium' or 'Narrow' Bandwidth, Command Register TXIMP bit set to '0' or '1' (same for Tx and Rx devices), with pseudo-random data. Note: S / N calculates as 20log10 ( Where:
Signal Voltage ) Voltage Noise
Signal Voltage is the measured VRMS of a random 4-level signal. Noise Voltage is the VRMS of a flat Gaussian noise signal having a bandwidth from a few Hz to twice the symbol rate e.g. to 9600Hz when measuring a 4800 symbol/sec (9600bps) system. Both signals are measured at the same point in the test circuit.
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
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MX919B PRELIMINARY INFORMATION
6.2
Packaging
Package Tolerances
A Z B E W L PIN 1 X Y CK H J P T
DIM. A B C E H J K L P T W X Y Z MIN.
0.597 (15.16) 0.286 (7.26) 0.093 (2.36) 0.390 (9.90) 0.003 (0.08) 0.013 (0.33) 0.036 (0.91)
TYP.
MAX.
0.613 (15.57) 0.299 (7.59) 0.105 (2.67) 0.419 (10.64) 0.020 (0.51) 0.020 (0.51) 0.046 (1.17)
ALTERNATIVE PIN LOCATION MARKING
0.050 (1.27) 0.016 (0.41) 0.050 (1.27) 0.009 (0.23) 45 0 5 5 10 7 0.0125 (0.32)
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX919BDW
A
Package Tolerances
Z B E L T X
DIM. A B C E H J L P T X Y Z MIN. TYP. MAX.
0.318 (8.07) 0.328 (8.33) 0.205 (5.20) 0.213 (5.39) 0.066 (1.67) 0.079 (2.00) 0.312 (7.90) 0.301 (7.65) 0.002 (0.05) 0.008 (0.21) 0.010 (0.25) 0.015 (0.38) 0.022 (0.55) 0.037 (0.95) 0.026 (0.65) 0.005 (0.13) 0.009 (0.22) 0 8 7 9 4 10
PIN 1
PIN 1 Y H J P
C
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX919BDS
(c)2001 MX*COM, INC.
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Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
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MX919B PRELIMINARY INFORMATION
E B Y DA
W
C K J W T H
Package Tolerances
DIM. A B C D E F G H J K P T W Y MIN. TYP. MAX.
0.409 (10.40) 0.380 (9.61) 0.409 (10.40) 0.380 (9.61) 0.146 (3.70) 0.128 (3.25) 0.417 (10.60) 0.435 (11.05) 0.417 (10.60) 0.435 (11.05) 0.250 (6.35) 0.250 (6.35) 0.023 (0.58) 0.018 (0.45) 0.022 (0.55) 0.047 (1.19) 0.048 (1.22) 0.049 (1.24) 0.051 (1.30) 0.006 (0.152) 0.009 (0.22) 30 45 6
PIN 1 P
G F
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 32: 24-pin PLCC Mechanical Outline : Order as part no. MX919BLH
A
Package Tolerances
DIM. A B C E E1 H J J1 K L P T Y MIN. TYP. MAX.
1.270 (32.26) 1.200 (30.48) 0.555 (14.04) 0.500 (12.70) 0.151 (3.84) 0.220 (5.59) 0.600 (15.24) 0.670 (17.02) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 0.121 (3.07) 0.160 (4.05) 0.100 (2.54) 0.008 (0.20) 0.015 (0.38) 7 NOTE : All dimensions in inches (mm.) Angles are in degrees
B
E1
Y
E
PIN1
T
K H L
C
J
J1
P
Figure 33: 24-pin PDIP Mechanical Outline: Order as part no. MX919BP
(c)2001 MX*COM, INC.
www.mxcom.com
Tele: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480170.003
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All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking On CML Microcircuits (USA) products, the `MX-COM' textual logo is being replaced by a `CML' textual logo.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/2 May 2002

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